1. Field of the Invention
The present invention relates to a data output buffer, and in particular, to a clock signal control apparatus for a data output buffer.
2. Background of the Related Art
As shown in FIG. 1, a related art clock signal control apparatus includes a clock controller 10 and a data output buffer 12. The clock controller delays an inputted clock signal CLOCK for a predetermined time and generates a clock signal CLKDO and an output enable signal OUTEN.sub.-- b. The data output buffer 11 receives a data DATA, buffers the data DATA in accordance with the clock signal CLKDO and the output enable signal OUTEN.sub.-- b, and generates an output signal OUTPUT.
As shown in FIG. 2, the data output buffer 11 includes a data latch unit 20 for latching the data DATA at a rising edge of the clock signal CLOCK, an output enable unit 21 for determining the output of the data DATA from the data latch unit 20 in accordance with the output enable signal OUTEN.sub.-- b and an output driving unit 22. The output driving unit 22 is driven by the output signal from the output enable unit 21 to generate the output signal OUTPUT.
The data latch unit 20 includes an inverter 20a for inverting the clock signal CLKDO to generate a clock signal CA, an inverter 20b for inverting the clock signal CA from the inverter 20a to generate a clock signal CB and a transmission gate 20c for passing the data DATA in accordance with the clock signal CB from the inverter 20b and the clock signal CA from the inverter 20a. Reverse-connected parallel inverters 20d and 20e are for latching the output signal from the transmission gate 20c. A transmission gate 20f is for switching the output signal from the inverter 20d in accordance with a clock signal CA and a clock signal CB. Inverters 20g and 20h are for sequentially inverting the output signal from the transmission gate 20f.
The output enable unit 21 includes an inverter 21c for inverting the output enable signal OUTEN.sub.-- b. A NAND-gate 21a NANDs the output signal from the inverter 21c and the output signal from the inverter 20g of the data latch unit 20. A NOR-gate 21b NORs the output enable signal OUTEN.sub.-- b and the output signal from the inverter 20g of the data latch unit 20.
The output driving unit 22 includes a PMOS transistor 22a having a gate that receives the output signal from the NAND-gate 21a of the output enable unit 21, a source that receives a power supply voltage VCC, and a drain that generates the output signal OUTPUT. An NMOS transistor 22b has a drain coupled to the drain of the PMOS transistor 22a, a gate that receives the output signal from the NOR-gate 21b of the output enable unit 21, and a source coupled to a ground voltage VSS.
A plurality of data output buffers 11 are provided in a dynamic random access memory (DRAM). Each data output buffer 11 receives an allocated data signal and is controlled in accordance with the output enable signal OUTEN.sub.-- b and the clock signal CLKDO.
The operation of the related art clock signal controller 10 and data output buffer 11 will now be described. The clock controller 10 delays the clock signal CLOCK shown in FIG. 3A for a predetermined time and outputs the delayed clock signal CLKDO as shown in FIG. 3B to the data output buffer 11. At this time, the clock controller 10 outputs the output enable signal OUTEN.sub.-- b, as shown in FIG. 3C, to the output enable unit 21 of the data output buffer 11. In addition, when the delayed clock signal CLKDO is low level, the transmission gate 20c turns on and the data DATA shown in FIG. 3D is passed through the transmission gate 20c and is latched by the inverters 20d and 20e. As shown in FIG. 3C, when the output enable signal OUTEN.sub.-- b is transited to a low level, the NAND-gate 21a of the output enable unit 21 converts its output signal from a high impedance low state to a high state as the high state data DATA latched by the inverters 20g and 20h is transmitted to the output driving unit 22.
When the delayed clock signal CLKDO is transited to a high level after the output enable signal OUTEN.sub.-- b is transited to a low level, the transmission gate 20c is turned off, and the transmission gate 20f is turned on. Thus, the data DATA latched by the inverters 20d and 20e is latched by the inverters 20g and 20h , which changes the level of the output of the inverter 20g to a low level.
Therefore, as the outputs from the NAND-gate 21a and the NOR-gate 21b become high level, the PMOS transistor 22a is turned off, and the NMOS transistor 22b is turned on. Accordingly, the output OUTPUT becomes a low level. Thus, the output driving unit 22 buffers the data DATA.
However, the related art clock signal control apparatus has various disadvantages. The related art data output buffer 11 sets the maintaining time of the output signal OUTPUT to be shorter by about 1.about.2 ns than the data access time tAC in order to satisfy the data access time tAC by the clock signal CLOCK of a high frequency. As shown in FIG. 3E, V.sub.OH is an output high voltage and V.sub.OL is an output low voltage. Thus, the tOH is the time from the rising edge of the clock pulse to when the output voltage goes low (e.g., V.sub.OL). The tAC is the time from the rising edge of the clock pulse to when the output voltage goes high (e.g., V.sub.OH. However, the maintaining time tOH is not changed even though the frequency of the clock signal CLOCK is lowered. Thus, even when the memory is driven by a low frequency clock signal CLOCK, the margin with respect to the latch time of the data DATA is not improved compared to the high frequency clock signal CLOCK. In addition, in the related art data output buffer 11, it is not possible to satisfy the condition of the data access time tAC by using a clock signal CLOCK of a predetermined high frequency.